/[projet1]/public/oric/demos/OricTech/code/sector_1-jasmin.asm
Defence Force logotype

Diff of /public/oric/demos/OricTech/code/sector_1-jasmin.asm

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 1396 by dbug, Sun May 31 12:03:16 2015 UTC revision 1397 by dbug, Sun Apr 9 10:42:35 2017 UTC
# Line 1  Line 1 
1  ;  ;
2  ; This part of the code is a bit tricky: Basically the Atmos with Microdisc and the Telestrat despite using a similar boot  ; This is the bootsector for the Jasmin drives.
3  ; loading system are actually loading the boot sector at different addresses.  ; No particular magic to do here, all the versions of the Jasmin system load the boot sector in page 4,
4  ;  ; so we can just assemble the bootsector code using $400 as the base address
 ; Since the 6502 is not particularly well equiped to handle code that can be loaded at any address we had to find a trick.  
 ; What we are doing is to make the code run at a particular address, and have a small module that makes sure that it is  
 ; moved at the correct place wherever it was loaded in first place. That makes the code a lot easier to write :)  
5  ;  ;
6  ; Warning: This whole code CANNOT be more than 256 bytes (ie: the size of the sector)  ; Warning: This whole code CANNOT be more than 256 bytes (ie: the size of the sector)
 ;  
 ; The bootloader will be placed in the screen area because we know that this is not going to be used by the operating system.  
 ; By chosing an address in HIRES area, we also guarantee that it will not be visible on the screen (the Oric boots in TEXT).  
 ;  
 #define FINAL_ADRESS    $a000+50*40  
7    
8    #define FDC_command_register    $03f4
9    #define FDC_status_register             $03f4
10    #define FDC_track_register              $03f5
11    #define FDC_sector_register             $03f6
12    #define FDC_data                                $03f7
13    #define FDC_flags                               $03f8
14    #define FDC_drq                 $03FC  
15    
16    #define FDC_ovl_control         $03FA
17    #define FDC_rom_control         $03FB
18    
19    #define CMD_ReadSector                  $8c
20    #define CMD_Seek                                $1F
21    
22  #define OPCODE_RTS                              $60  #define wait_status_floppy 30
23    
24  #define JASMIN_LOADER  #include "floppy_description.h"       ; This file is generated by the floppy builder
 #include "disk_info.h"  
25    
26          .zero          .zero
27                    
# Line 28  retry_counter          .dsb 1  ; Number of attemp Line 32  retry_counter          .dsb 1  ; Number of attemp
32          .text          .text
33    
34          *=$400          *=$400
35      jmp $440 ;.byt $01,$00,$00  
36        jmp JasminStart ;.byt $01,$00,$00
37          .byt $00,$00,$00,$00,$00,$20,$20,$20,$20,$20,$20,$20,$20          .byt $00,$00,$00,$00,$00,$20,$20,$20,$20,$20,$20,$20,$20
38          .byt $00,$00,$03,$00,$00,$00,$01,$00,$53,$45,$44,$4F,$52,$49,$43,$20          .byt $00,$00,$03,$00,$00,$00,$01,$00,$53,$45,$44,$4F,$52,$49,$43,$20
39          .byt $20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20          .byt $20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20
40          .byt $20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20          .byt $20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20
41    
 ; FDC_flags  
 ;#define FDC_flags                              $0314    
 ;                                                                               |xxxxxxxx| Write  
 ;                                        ||||||||  
 ;                                        ||||||||_____bit 0: enable FDC INTRQ to appear on read location $0314 and to drive cpu IRQ  
 ;                                        |||||||_____ bit 1: ROMDIS (active low). When 0, internal Basic rom is disabled.  
 ;                                        ||||||______ bit 2: along with bit 3, selects the data separator clock divisor            (1: double density, 0: single-density)  
 ;                                        |||||_______ bit 3: double density enable (0: double density, 1: single density)  
 ;                                        ||||________ bit 4: side select  
 ;                                        |||_________ bits 56: drive select (0 to 3)  
 ;                                        |___________ bit 7: Eprom select (active low)  
 ;  
 ;                                        %10000101 -> Eprom deselected, double density, ROM disabled, irq enabled  
 ;                                        %10000001 ->  
   
42  JasminStart  JasminStart
43          ;jmp JasminStart          ;jmp JasminStart
44          ;          ;
# Line 62  JasminStart Line 52  JasminStart
52    
53          ; Enable Overlay ram          ; Enable Overlay ram
54          lda #1          lda #1
55          sta $03FA ; Enable Overlay          sta FDC_ovl_control ; Enable Overlay
56          lda #1          lda #1
57          sta $03FB ; Disable ROM          sta FDC_rom_control ; Disable ROM
58    
59    
60          ;          ;
# Line 85  read_one_sector Line 75  read_one_sector
75          ; then send a SEEK command to the FDC to move the head to          ; then send a SEEK command to the FDC to move the head to
76          ; the correct track.          ; the correct track.
77          ;          ;
78          ldx #loader_track_position          ldx #FLOPPY_LOADER_TRACK
79          cpx FDC_track_register          cpx FDC_track_register
80          beq track_ok          beq track_ok
81                    
# Line 120  track_ok Line 110  track_ok
110    
111          ; Write the sector number in the FDC sector register          ; Write the sector number in the FDC sector register
112  __auto__sector_index  __auto__sector_index
113          lda #loader_sector_position          lda #FLOPPY_LOADER_SECTOR
114          sta FDC_sector_register ;      sta FDC_sector_register
115                    
         ; Interdire les IRQ du fdc ICI !  
         ;lda #%10000100                         ; on force les le Microdisk en side0, drive A ... Set le bit de données !!!  
         ;sta FDC_flags  
116                                                    
117          ;          ;
118          ; Send a READSECTOR command          ; Send a READSECTOR command
# Line 149  fetch_bytes_from_FDC Line 136  fetch_bytes_from_FDC
136          bmi fetch_bytes_from_FDC          bmi fetch_bytes_from_FDC
137          lda FDC_data          lda FDC_data
138  __auto_write_address  __auto_write_address
139          sta location_loader,y          sta FLOPPY_LOADER_ADDRESS,y
140    
141          iny          iny
142          bne fetch_bytes_from_FDC          bne fetch_bytes_from_FDC
# Line 175  sector_OK Line 162  sector_OK
162          lda #%10000001                  ; Disable the FDC (Eprom select + FDC Interrupt request)          lda #%10000001                  ; Disable the FDC (Eprom select + FDC Interrupt request)
163          sta FDC_flags          sta FDC_flags
164                    
165          ldx #FDC_OFFSET_JASMIN          ldx #1                      ; 1 = Jasmin initialisation code
166          jmp location_loader          jmp FLOPPY_LOADER_ADDRESS
   
167                    
168    sector_counter          .byt (($FFFF-FLOPPY_LOADER_ADDRESS)+1)/256
   
   
 sector_counter          .byt (($FFFF-location_loader)+1)/256  
   
169    
170  _END_  _END_
171    
   
   
 ; Type I commands  
 ;       The type I commands include the Restore, Seek, Step, Step-In and Step-  
 ;       Out commands. Each of the Type I commands contains a rate field r1 r0  
 ;       which determines the stepping motor rate.  
 ;               r1 r0 Stepping rate  
 ;                0  0    6 ms  
 ;                0  1   12 ms  
 ;                1  0   20 ms  
 ;                1  1   30 ms  
 ;       An optional verification of head position can be performed by settling  
 ;       bit 2 (V=1) in the command word. The track number from the first  
 ;       encountered ID Field is compared against the contents of the Track  
 ;       Register. If the track numbers compare (and the ID Field CRC is correct)  
 ;       the verify operation is complete and an INTRQ is generated with no  
 ;       errors.  
 ;        
 ; Seek  
 ;       This command assumes that the Track Register contains the track number  
 ;       of the current position of the head and the Data Register contains the  
 ;       desired track number. The FD179X will update the Track Register and  
 ;       issue stepping pulses in the appropriate direction until the contents of  
 ;       the Track Register are equal to the contents of the Data Register. An  
 ;       interrupt is generated at the completion of the command. Note: when  
 ;       using multiple drives, the track register must be updated for the drive  
 ;       selected before seeks are issued.  
   
 ;  
 ; Type II commands  
 ;       Type II commands are the Read Sector and Write Sector commands. Prior  
 ;       to loading the Type II command into the Command Register, the computer  
 ;       must load the Sector Register with the desired sector number. Upon  
 ;       receipt of the Type II command, the busy status bit is set. The FD179X  
 ;       must find an ID field with a matching Track number and Sector number,  
 ;       otherwise the Record not found status bit is set and the command is  
 ;       terminated with an interrupt. Each of the Type II commands contains an  
 ;       m flag which determines if multiple records (sectors) are to be read or  
 ;       written. If m=0, a single sector is read or written and an interrupt is  
 ;       generated at the completion of the command. If m=1, multiple records are  
 ;       read or written with the sector register internally updated so that an  
 ;       address verification can occur on the next record. The FD179X will  
 ;       continue to read or write multiple records and update the sector  
 ;       register in numerical ascending sequence until the sector register  
 ;       exceeds the number of sectors on the track or until the Force Interrupt  
 ;       command is loaded into the Command Register. The Type II commands for  
 ;       1791-94 also contain side select compare flags. When C=0 (bit 1), no  
 ;       comparison is made. When C=1, the LSB of the side number is read off the  
 ;       ID Field of the disk and compared with the contents of the S flag.  
 ;  
 ; Read Sector  
 ;       Upon receipt of the command, the head is loaded, the busy status bit set  
 ;       and when an ID field is encountered that has the correct track number,  
 ;       correct sector number, correct side number, and correct CRC, the data  
 ;       field is presented to the computer. An DRQ is generated each time a byte  
 ;       is transferred to the DR. At the end of the Read operation, the type of  
 ;       Data Address Mark encountered in the data field is recorded in the  
 ;       Status Register (bit 5).  
 ;  
   
   
 /*  
 From: http://www.metabarn.com/v1050/docs/v1050_ProgTechDoc.txt  
   
 During a command which performs a data transfer such as diskette  
 read or write, data must be read from or written to the diskettes  
 byte-by—byte via the Z-80A. This can be done either by polling  
 the WD1793 data request bit (DRQ, status bit 1) or by the DRQ  
 interrupt. Reading or writing the data register will reset both  
 the DRQ bit and interrupt. The total time between byte transfers  
 is 23 microseconds for 5" double density or 8" single density;  
 the polling loop or interrupt service routine must be shorter  
 than this to insure that no bytes are lost.  
   
 The diskette motors are turned on by resetting bit 6 of port A of  
 the miscellaneous 8255, and turned off by setting the same bit.  
 Our BIOS code turns the motors on, then leaves them on for two  
 seconds to save time in the case of multiple disk accesses.  
 After turning on the motors, you must wait 800 ms. to be sure  
 that the drives are up to speed before attempting to transfer  
 data. The Ready input of the WD1793 is supplied from pin 34 of  
 the drive interface; it indicates that the drive is loaded and  
 has made at least one revolution at > 50% of normal speed. Note  
 that the drive looks at the index pulse for this; if a hard-  
 sectored disk is inserted the results are invalid.  
   
 The reset line of the WD1793 is held in the reset mode by  
 hardware at power-on. A timing restriction is inherent in the  
 WD1793: after writing a command, the Z-80A must not read the  
 status register for 28 microseconds.  
   
 */  

Legend:
Removed from v.1396  
changed lines
  Added in v.1397

  ViewVC Help
Powered by ViewVC 1.1.26