/[projet1]/public/oric/demos/SlideShowDemo/code/sector_2-microdisc.asm
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Annotation of /public/oric/demos/SlideShowDemo/code/sector_2-microdisc.asm

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Revision 1046 - (hide annotations)
Sat Dec 21 13:50:30 2013 UTC (5 years, 11 months ago) by dbug
File size: 9948 byte(s)
Started Jasmin compatibility, abstracted the registers used.
1 dbug 1015 ;
2     ; This part of the code is a bit tricky: Basically the Atmos with Microdisc and the Telestrat despite using a similar boot
3     ; loading system are actually loading the boot sector at different addresses.
4     ;
5     ; Since the 6502 is not particularly well equiped to handle code that can be loaded at any address we had to find a trick.
6     ; What we are doing is to make the code run at a particular address, and have a small module that makes sure that it is
7     ; moved at the correct place wherever it was loaded in first place. That makes the code a lot easier to write :)
8     ;
9     ; Warning: This whole code CANNOT be more than 256 bytes (ie: the size of the sector)
10     ;
11     ; The bootloader will be placed in the screen area because we know that this is not going to be used by the operating system.
12     ; By chosing an address in HIRES area, we also guarantee that it will not be visible on the screen (the Oric boots in TEXT).
13     ;
14     #define FINAL_ADRESS $a000+50*40
15    
16    
17     #define OPCODE_RTS $60
18    
19 dbug 1046 #define MICRODISC_LOADER
20 dbug 1015 #include "disk_info.h"
21    
22     .zero
23    
24     *=$00
25    
26     retry_counter .dsb 1 ; Number of attempts at loading data (ie: not quite clear what happens when this fails...)
27    
28    
29     .text
30    
31     ;
32     ; These are the 23 header bytes that goes before the actual executable part of the bootsector
33     ;
34     .byt $00,$00,$FF,$00,$D0,$9F,$D0,$9F,$02,$B9,$01,$00,$FF,$00,$00,$B9,$E4,$B9,$00,$00,$E6,$12,$00
35    
36     .text
37    
38     ;
39     ; Here starts the actual executable part, maximum available size is 233 bytes (256-23)
40     ;
41    
42     ;
43     ; Try to find the load address
44     ;
45     sei ; Disable interruptions
46    
47     lda #OPCODE_RTS
48     sta $00 ; Write in $00 Page => take one less byte
49     jsr $0000 ; JSR on the RTS immediately return.
50    
51     ;
52     ; Compute the absolute address of where the code we want to copy begins,
53     ; and save it in zero page ($00 and $01)
54     ;
55     _start_relocator_
56     tsx ; Get stack offset
57     dex
58     clc
59     lda $0100,x ; Get LOW adress byte
60     adc #<(_end_relocator_-_start_relocator_+1)
61     sta $00
62     lda $0101,x ; Get HIGH adress byte
63     adc #>(_end_relocator_-_start_relocator_+1)
64     sta $01
65    
66     ; Now $00 and $01 contain the adress of LABEL
67     ; We can now copy the whole code to it's new
68     ; location
69     ldy #0
70     copy_loop
71     lda ($00),y
72     sta FINAL_ADRESS,y
73     iny
74     cpy _END_-_BEGIN_
75     bne copy_loop
76    
77     jmp FINAL_ADRESS
78     _end_relocator_
79    
80    
81     ;
82     ; Here is some code compiled at a fixed adress in memory.
83     ;
84    
85     *=FINAL_ADRESS
86    
87     _BEGIN_
88     ;
89     ; Read sector data
90     ;
91     ldy #4
92     sty retry_counter
93     read_sectors_loop
94    
95     readretryloop
96     nop
97     nop
98     nop
99    
100     read_one_sector
101     ;
102     ; Check if we are on the correct track already and if not
103     ; then send a SEEK command to the FDC to move the head to
104     ; the correct track.
105     ;
106     ldx #loader_track_position
107     cpx FDC_track_register
108     beq track_ok
109    
110     ; Write the track number in the FDC data register
111     stx FDC_data
112    
113     wait_drive2
114     lda $318 ; We are waiting for the drive maybe not useful if drive is ready after the eprom boot
115     bmi wait_drive2
116    
117     ;
118     ; Send a SEEK command (change track)
119     ;
120     lda #CMD_Seek
121     sta FDC_command_register
122     jsr WaitCompletion
123     track_ok
124    
125     ; Write the sector number in the FDC sector register
126     __auto__sector_index
127     lda #loader_sector_position
128     sta FDC_sector_register ;
129    
130     ; Interdire les IRQ du fdc ICI !
131     ;lda #%10000101 ; on force les le Microdisk en side0, drive A ... Set le bit de données !!!
132     lda #%10000100 ; on force les le Microdisk en side0, drive A ... Set le bit de données !!!
133     sta MICRODISC
134    
135     ;
136     ; Send a READSECTOR command
137     ;
138     lda #CMD_ReadSector
139     sta FDC_command_register
140    
141     ldy #wait_status_floppy
142     waitcommand
143     nop ; Not useful but for old Floppy drive maybe
144     nop ; Not useful but for old Floppy drive maybe
145     dey
146     bne waitcommand
147    
148     ;
149     ; Read the sector data
150     ;
151     ldy #0
152     fetch_bytes_from_FDC
153     lda $0318
154     bmi fetch_bytes_from_FDC
155     lda $0313
156     __auto_write_address
157     sta location_loader,y
158    
159     iny
160     bne fetch_bytes_from_FDC
161     ; Done loading the sector
162    
163     lda FDC_status_register
164     and #$1C
165    
166     beq sector_OK
167     dec retry_counter
168     bne readretryloop
169    
170     sector_OK
171     inc __auto__sector_index+1
172     inc __auto_write_address+2
173     dec sector_counter
174     bne read_sectors_loop
175    
176     ;
177     ; Data successfully loader (we hope)
178     ;
179     sei
180     lda #%10000001 ; Disable the FDC (Eprom select + FDC Interrupt request)
181     sta MICRODISC
182    
183     jmp location_loader
184    
185    
186     ;
187     ; Command words should only be loaded in the Command Register when the
188     ; Busy status bit is off (Status bit 0). The one exception is the Force
189     ; Interrupt command. Whenever a command is being executed, the Busy status
190     ; bit is set. When a command is completed, an interrupt is generated and
191     ; the busy status bit is reset. The Status Register indicates whethter the
192     ; completed command encountered an error or was fault free. For ease of
193     ; discussion, commands are divided into four types (I, II, III, IV).
194     ;
195     WaitCompletion
196     .(
197     ldy #4
198     r_wait_completion
199     dey
200     bne r_wait_completion
201     r2_wait_completion
202     lda FDC_status_register
203     lsr
204     bcs r2_wait_completion
205     asl
206     rts
207     .)
208    
209    
210 dbug 1024 sector_counter .byt (($FFFF-location_loader)+1)/256
211 dbug 1015
212    
213     _END_
214    
215    
216    
217     ; Type I commands
218     ; The type I commands include the Restore, Seek, Step, Step-In and Step-
219     ; Out commands. Each of the Type I commands contains a rate field r1 r0
220     ; which determines the stepping motor rate.
221     ; r1 r0 Stepping rate
222     ; 0 0 6 ms
223     ; 0 1 12 ms
224     ; 1 0 20 ms
225     ; 1 1 30 ms
226     ; An optional verification of head position can be performed by settling
227     ; bit 2 (V=1) in the command word. The track number from the first
228     ; encountered ID Field is compared against the contents of the Track
229     ; Register. If the track numbers compare (and the ID Field CRC is correct)
230     ; the verify operation is complete and an INTRQ is generated with no
231     ; errors.
232     ;
233     ; Seek
234     ; This command assumes that the Track Register contains the track number
235     ; of the current position of the head and the Data Register contains the
236     ; desired track number. The FD179X will update the Track Register and
237     ; issue stepping pulses in the appropriate direction until the contents of
238     ; the Track Register are equal to the contents of the Data Register. An
239     ; interrupt is generated at the completion of the command. Note: when
240     ; using multiple drives, the track register must be updated for the drive
241     ; selected before seeks are issued.
242    
243     ;
244     ; Type II commands
245     ; Type II commands are the Read Sector and Write Sector commands. Prior
246     ; to loading the Type II command into the Command Register, the computer
247     ; must load the Sector Register with the desired sector number. Upon
248     ; receipt of the Type II command, the busy status bit is set. The FD179X
249     ; must find an ID field with a matching Track number and Sector number,
250     ; otherwise the Record not found status bit is set and the command is
251     ; terminated with an interrupt. Each of the Type II commands contains an
252     ; m flag which determines if multiple records (sectors) are to be read or
253     ; written. If m=0, a single sector is read or written and an interrupt is
254     ; generated at the completion of the command. If m=1, multiple records are
255     ; read or written with the sector register internally updated so that an
256     ; address verification can occur on the next record. The FD179X will
257     ; continue to read or write multiple records and update the sector
258     ; register in numerical ascending sequence until the sector register
259     ; exceeds the number of sectors on the track or until the Force Interrupt
260     ; command is loaded into the Command Register. The Type II commands for
261     ; 1791-94 also contain side select compare flags. When C=0 (bit 1), no
262     ; comparison is made. When C=1, the LSB of the side number is read off the
263     ; ID Field of the disk and compared with the contents of the S flag.
264     ;
265     ; Read Sector
266     ; Upon receipt of the command, the head is loaded, the busy status bit set
267     ; and when an ID field is encountered that has the correct track number,
268     ; correct sector number, correct side number, and correct CRC, the data
269     ; field is presented to the computer. An DRQ is generated each time a byte
270     ; is transferred to the DR. At the end of the Read operation, the type of
271     ; Data Address Mark encountered in the data field is recorded in the
272     ; Status Register (bit 5).
273     ;
274    
275    
276     /*
277     From: http://www.metabarn.com/v1050/docs/v1050_ProgTechDoc.txt
278    
279     During a command which performs a data transfer such as diskette
280     read or write, data must be read from or written to the diskettes
281     byte-by—byte via the Z-80A. This can be done either by polling
282     the WD1793 data request bit (DRQ, status bit 1) or by the DRQ
283     interrupt. Reading or writing the data register will reset both
284     the DRQ bit and interrupt. The total time between byte transfers
285     is 23 microseconds for 5" double density or 8" single density;
286     the polling loop or interrupt service routine must be shorter
287     than this to insure that no bytes are lost.
288    
289     The diskette motors are turned on by resetting bit 6 of port A of
290     the miscellaneous 8255, and turned off by setting the same bit.
291     Our BIOS code turns the motors on, then leaves them on for two
292     seconds to save time in the case of multiple disk accesses.
293     After turning on the motors, you must wait 800 ms. to be sure
294     that the drives are up to speed before attempting to transfer
295     data. The Ready input of the WD1793 is supplied from pin 34 of
296     the drive interface; it indicates that the drive is loaded and
297     has made at least one revolution at > 50% of normal speed. Note
298     that the drive looks at the index pulse for this; if a hard-
299     sectored disk is inserted the results are invalid.
300    
301     The reset line of the WD1793 is held in the reset mode by
302     hardware at power-on. A timing restriction is inherent in the
303     WD1793: after writing a command, the Z-80A must not read the
304     status register for 28 microseconds.
305    
306     */

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