/[projet1]/public/oric/hardware/cumulus/cpld/Cumulus.VHDL
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Contents of /public/oric/hardware/cumulus/cpld/Cumulus.VHDL

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Revision 425 - (show annotations)
Mon Jan 24 12:22:08 2011 UTC (9 years, 2 months ago) by retromaster
File size: 10058 byte(s)
Initial add of CPLD sources.
1 -- Cumulus CPLD Core
2 -- Top Level Entity
3 -- Copyright 2010 Retromaster
4 --
5 -- This file is part of Cumulus CPLD Core.
6 --
7 -- Cumulus CPLD Core is free software: you can redistribute it and/or modify
8 -- it under the terms of the GNU General Public License as published by
9 -- the Free Software Foundation, either version 3 of the License,
10 -- or any later version.
11 --
12 -- Cumulus CPLD Core is distributed in the hope that it will be useful,
13 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
14 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 -- GNU General Public License for more details.
16 --
17 -- You should have received a copy of the GNU General Public License
18 -- along with Cumulus CPLD Core. If not, see <http://www.gnu.org/licenses/>.
19 --
20
21 library IEEE;
22 use IEEE.STD_LOGIC_1164.ALL;
23 use IEEE.STD_LOGIC_ARITH.ALL;
24 use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26 entity Cumulus is
27 port(
28 CLK: in std_logic; -- 32 Mhz input clock
29
30 -- Oric Expansion Port Signals
31 D: inout std_logic_vector(7 downto 0); -- 6502 Data Bus
32 A: in std_logic_vector(15 downto 0); -- 6502 Address Bus
33 RnW: in std_logic; -- 6502 Read-/Write
34 nIRQ: out std_logic; -- 6502 /IRQ
35 PH2: in std_logic; -- 6502 PH2
36 nROMDIS: out std_logic; -- Oric ROM Disable
37 nMAP: out std_logic; -- Oric MAP
38 IO: in std_logic; -- Oric I/O
39 IOCTRL: out std_logic; -- Oric I/O Control
40 nHOSTRST: out std_logic; -- Oric RESET
41
42 -- Data Bus Buffer Control Signals
43 nOE: out std_logic; -- Output Enable
44 DIR: out std_logic; -- Direction
45
46 -- CPLD-MCU Interface
47 nMWE: in std_logic; -- Write Enable
48 nMOE: in std_logic; -- Output Enable
49 MFS: in std_logic_vector(2 downto 0); -- Function Select
50 MD: inout std_logic_vector(7 downto 0); -- Data Bus
51 nMCRQ: out std_logic; -- Command Request
52
53 -- Additional MCU Interface Lines
54 nRESET: in std_logic; -- RESET from MCU
55 DSEL: out std_logic_vector(1 downto 0); -- Drive Select
56 SSEL: out std_logic; -- Side Select
57
58 -- EEPROM Control Lines.
59 nECE: out std_logic; -- Chip Enable
60 nEOE: out std_logic; -- Output Enable
61 EA13: out std_logic; -- Address
62 EA14: out std_logic;
63 );
64 end Cumulus;
65
66 architecture Behavioral of Cumulus is
67
68 component WD1793
69 port( -- CPU Interface
70 nCS: in std_logic; -- Chip Select
71 nRE: in std_logic; -- Read Enable
72 nWE: in std_logic; -- Write Enable
73 CLK: in std_logic; -- System Clock
74 A: in std_logic_vector(1 downto 0); -- Register Select
75 DALin: in std_logic_vector(7 downto 0); -- Data Bus
76 DALout: out std_logic_vector(7 downto 0); -- Data Bus
77 DRQ: out std_logic; -- Data Request
78 IRQ: out std_logic; -- Interrupt Request
79 nMR: in std_logic; -- Master Reset
80
81 -- MCU Interface
82 nMWE: in std_logic; -- Write Enable
83 nMOE: in std_logic; -- Output Enable
84 MFS: in std_logic_vector(2 downto 0); -- Function Select
85 MD: inout std_logic_vector(7 downto 0); -- Data Bus
86 nMCRQ: out std_logic -- Command Request
87 );
88 end component;
89
90 signal fdc_nCS: std_logic;
91 signal fdc_nRE: std_logic;
92 signal fdc_nWE: std_logic;
93 signal fdc_CLK: std_logic;
94 signal fdc_A: std_logic_vector(1 downto 0);
95 signal fdc_DALin: std_logic_vector(7 downto 0);
96 signal fdc_DALout: std_logic_vector(7 downto 0);
97 signal fdc_DRQ: std_logic;
98 signal fdc_IRQ: std_logic;
99
100 signal sel: std_logic;
101 signal u16k: std_logic;
102 signal inECE: std_logic;
103 signal inROMDIS: std_logic;
104 signal iDIR: std_logic;
105
106 -- Control Register
107 signal nROMEN: std_logic; -- ROM Enable
108 signal IRQEN: std_logic; -- IRQ Enable
109
110 signal inMCRQ: std_logic;
111
112 signal DBG_cntr: std_logic_vector(1 downto 0);
113 signal DBG_signal: std_logic;
114
115 signal PH2_1: std_logic;
116 signal PH2_2: std_logic;
117 signal PH2_3: std_logic;
118 signal PH2_old: std_logic_vector(3 downto 0);
119 signal PH2_cntr: std_logic_vector(4 downto 0);
120
121 begin
122
123 FDC: WD1793
124 port map(fdc_nCS, fdc_nRE, fdc_nWE, fdc_CLK, fdc_A, fdc_DALin, fdc_DALout, fdc_DRQ, fdc_IRQ, nRESET, DBG2, nMWE, nMOE, MFS, MD, inMCRQ);
125
126 -- Reset
127 nHOSTRST <= '0' when nRESET = '0' else 'Z';
128
129 -- Select signal (Address Range 031-)
130 sel <= '1' when A(7 downto 4) = "0001" and IO = '0' and A(3 downto 2) /= "11" else '0';
131
132 -- WD1793 Signals
133 fdc_A <= A(1 downto 0);
134 fdc_nCS <= '0' when sel = '1' and A(3 downto 2) = "00" else '1';
135 fdc_nRE <= IO or not RnW;
136 fdc_nWE <= IO or RnW;
137 fdc_CLK <= not PH2_2;
138 fdc_DALin <= D;
139
140 -- ORIC Expansion Port Signals
141 IOCTRL <= '0' when sel = '1' else 'Z';
142 nROMDIS <= '0' when inROMDIS = '0' else 'Z';
143 nIRQ <= '0' when fdc_IRQ = '1' and IRQEN = '1' else 'Z';
144
145 -- EEPROM Control Signals
146 nEOE <= PH2_1 or not RnW;
147 u16k <= '1' when (inROMDIS = '0') and (A(14) = '1') and (A(15) = '1') else '0';
148 inECE <= not (A(13) and u16k and not nROMEN);
149 nECE <= inECE;
150 nMAP <= '0' when (PH2_2 and inECE and u16k) = '1' else 'Z';
151 EA13 <= '0';
152 EA14 <= '0';
153
154 nMCRQ <= inMCRQ;
155
156 DIR <= iDIR;
157 iDIR <= RnW;
158
159 -- Data Bus Control.
160 process (iDIR, fdc_DALout, fdc_DRQ, fdc_IRQ, fdc_nRE, A)
161 begin
162 if iDIR = '1' then
163 if A(3 downto 2) = "10" then
164 D <= (not fdc_DRQ) & "-------";
165 elsif A(3 downto 2) = "01" then
166 D <= (not fdc_IRQ) & "-------";
167 elsif fdc_nRE = '0' and fdc_nCS = '0' then
168 D <= fdc_DALout;
169 else
170 D <= "--------";
171 end if;
172 else
173 D <= "ZZZZZZZZ";
174 end if;
175 end process;
176
177 nOE <= '0' when sel = '1' and PH2 = '1' else '1';
178
179 -- Control Register.
180 process (sel, A, RnW, D)
181 begin
182 if nRESET = '0' then
183 nROMEN <= '0';
184 DSEL <= "00";
185 SSEL <= '0';
186 inROMDIS <= '0';
187 IRQEN <= '0';
188 elsif falling_edge(PH2_2) then
189 if sel = '1' and A(3 downto 2) = "01" and RnW = '0' then
190 nROMEN <= D(7);
191 DSEL <= D(6 downto 5);
192 SSEL <= D(4);
193 inROMDIS <= D(1);
194 IRQEN <= D(0);
195 end if;
196 end if;
197 end process;
198
199 -- PH2 derived clocks.
200 process (PH2, CLK)
201 begin
202 if nRESET = '0' then
203 PH2_cntr <= "00000";
204 elsif falling_edge(CLK) then
205 PH2_old <= PH2_old(2 downto 0) & PH2;
206 if (PH2_old = "1111") and (PH2 = '0') then
207 PH2_cntr <= "00000";
208 PH2_1 <= '1';
209 else
210 PH2_cntr <= PH2_cntr + 1;
211 if (PH2_cntr = "10000") then
212 PH2_1 <= '0';
213 PH2_2 <= '1';
214 elsif (PH2_cntr = "10111") then
215 PH2_3 <= '1';
216 elsif (PH2_cntr = "11100") then
217 PH2_2 <= '0';
218 elsif (PH2_cntr = "11101") then
219 PH2_3 <= '0';
220 end if;
221 end if;
222 end if;
223 end process;
224
225 end Behavioral;
226

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