/[projet1]/public/oric/hardware/cumulus/cpld/WD1793.VHDL
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Contents of /public/oric/hardware/cumulus/cpld/WD1793.VHDL

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Revision 425 - (show annotations)
Mon Jan 24 12:22:08 2011 UTC (9 years, 2 months ago) by retromaster
File size: 7861 byte(s)
Initial add of CPLD sources.
1 -- Cumulus CPLD Core
2 -- WD1793 Entity
3 -- Copyright 2010 Retromaster
4 --
5 -- This file is part of Cumulus CPLD Core.
6 --
7 -- Cumulus CPLD Core is free software: you can redistribute it and/or modify
8 -- it under the terms of the GNU General Public License as published by
9 -- the Free Software Foundation, either version 3 of the License,
10 -- or any later version.
11 --
12 -- Cumulus CPLD Core is distributed in the hope that it will be useful,
13 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
14 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 -- GNU General Public License for more details.
16 --
17 -- You should have received a copy of the GNU General Public License
18 -- along with Cumulus CPLD Core. If not, see <http://www.gnu.org/licenses/>.
19 --
20
21 -- Open Issues:
22 --
23 -- 1. Data Request handling: Asynchronous Set/Resets?
24 -- 2. Not Ready Status Bit Reset when /MR active.
25 -- 3. Anything else affected by /MR?
26 -- 4. Track Register only contains 7 bits.
27
28 library IEEE;
29 use IEEE.STD_LOGIC_1164.ALL;
30 use IEEE.STD_LOGIC_ARITH.ALL;
31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
32
33 entity WD1793 is
34 port( -- CPU Interface
35 nCS: in std_logic; -- Chip Select
36 nRE: in std_logic; -- Read Enable
37 nWE: in std_logic; -- Write Enable
38 CLK: in std_logic; -- System Clock
39 A: in std_logic_vector(1 downto 0); -- Register Select
40 DALin: in std_logic_vector(7 downto 0); -- Data Bus
41 DALout: out std_logic_vector(7 downto 0); -- Data Bus
42 DRQ: out std_logic; -- Data Request
43 IRQ: out std_logic; -- Interrupt Request
44 nMR: in std_logic; -- Master Reset
45
46 -- MCU Interface
47 nMWE: in std_logic; -- Write Enable
48 nMOE: in std_logic; -- Output Enable
49 MFS: in std_logic_vector(2 downto 0); -- Function Select
50 MD: inout std_logic_vector(7 downto 0); -- Data Bus
51 nMCRQ: out std_logic -- Command Request
52 );
53 end WD1793;
54
55 architecture Behavioral of WD1793 is
56
57 signal data: std_logic_vector(7 downto 0);
58 signal track: std_logic_vector(6 downto 0);
59 signal sector: std_logic_vector(7 downto 0);
60 signal command: std_logic_vector(7 downto 0);
61 signal status: std_logic_vector(7 downto 0);
62 signal MST: std_logic_vector(6 downto 0);
63
64 -- Status
65 signal busy: std_logic;
66 signal lostData: std_logic;
67 signal dataRequest: std_logic;
68 signal commandRequest: std_logic;
69
70 begin
71
72 -- DRQ Output
73 DRQ <= dataRequest;
74
75 -- nMCRQ Output
76 nMCRQ <= not commandRequest;
77
78 -- MCU Command Request
79 process(nCS, nWE, A, nMOE, MFS)
80 begin
81 if rising_edge(CLK) then
82 if nWE = '0' and nCS = '0' and A = "00" then
83 commandRequest <= '1';
84 elsif nMWE = '0' and MFS = "110" then
85 commandRequest <= '0';
86 end if;
87 end if;
88 end process;
89
90 -- Status output.
91 process(command, MST, lostData, dataRequest, busy)
92 begin
93 if command(7) = '0' or command(7 downto 4) = "1101" then
94 status <= MST & busy;
95 else
96 status <= MST(6 downto 2) & lostData & dataRequest & busy;
97 end if;
98 end process;
99
100 process(nCS, nRE, A, track, sector, data, status)
101 begin
102 -- DAL Read Control.
103 if nCS = '0' and nRE = '0' then
104 if A = "00" then
105 DALout <= status;
106 elsif A = "01" then
107 DALout <= "0" & track;
108 elsif A = "10" then
109 DALout <= sector;
110 else
111 DALout <= data;
112 end if;
113 else
114 --DAL <= "ZZZZZZZZ";
115 DALout <= "--------";
116 end if;
117
118 end process;
119
120 process(CLK, nCS, nWE, A, DALin, nMWE, MFS, MD, nRE, commandRequest)
121 begin
122
123 -- Command Register
124 if nMR = '0' then
125 command <= "00000011";
126 elsif rising_edge(CLK) and nCS = '0' and nWE = '0' and A = "00" then
127 command <= DALin;
128 end if;
129
130 -- Track Register
131 if rising_edge(CLK) then
132 if nCS = '0' and nWE = '0' and A = "01" then
133 track <= DALin(6 downto 0);
134 elsif nMWE = '0' and MFS = "101" then
135 track <= MD(6 downto 0);
136 end if;
137 end if;
138
139 -- Sector Register
140 if nMR = '0' then
141 sector <= "00000001";
142 elsif rising_edge(CLK) then
143 if nMWE = '0' and MFS = "000" then
144 sector <= MD;
145 elsif nCS = '0' and nWE = '0' and A = "10" then
146 sector <= DALin;
147 end if;
148 end if;
149
150 -- Data Register
151 if rising_edge(CLK) then
152 if nCS = '0' and nWE = '0' and A = "11" then
153 data <= DALin;
154 elsif nMWE = '0' and MFS = "011" then
155 data <= MD;
156 end if;
157 end if;
158
159 -- BUSY handling
160 if rising_edge(CLK) then
161 -- Command loaded, busy set.
162 if nCS = '0' and nWE = '0' and A = "00" then
163 busy <= '1';
164 elsif nMWE = '0' and MFS = "010" then
165 busy <= '0';
166 end if;
167 end if;
168
169 -- IRQ handling
170 if rising_edge(CLK) then
171 if nCS = '0' and nRE = '0' and A = "00" then
172 -- Status register read.
173 IRQ <= '0';
174 elsif nMWE = '0' and MFS = "010" then
175 IRQ <= '1';
176 end if;
177 end if;
178
179 -- Data Request
180 if rising_edge(CLK) then
181 if nCS = '0' and (nRE = '0' or nWE = '0') and A = "11" then
182 -- CPU access.
183 dataRequest <= '0';
184 elsif nMWE = '0' and MFS = "001" then
185 -- Data Request from MCU.
186 dataRequest <= '1';
187 end if;
188 end if;
189
190 -- Lost Data
191 -- if commandRequest = '1' then
192 -- lostData <= '0';
193 -- elsif rising_edge(CLK) and nMWE = '0' and MFS = "001" and dataRequest = '1' then
194 -- lostData <= '1';
195 -- end if;
196 lostData <= '0';
197
198 -- Status Bits
199 if rising_edge(CLK) and nMWE = '0' and MFS = "100" then
200 MST <= MD(7 downto 1);
201 end if;
202
203 end process;
204
205 -- MCU Bus Read Control
206 process(MFS, nMOE, track, data, sector, command)
207 begin
208 if nMOE = '0' then
209 if MFS = "000" then
210 MD <= command;
211 elsif MFS = "001" then
212 MD <= "0" & track;
213 elsif MFS = "010" then
214 MD <= sector;
215 elsif MFS = "011" then
216 MD <= data;
217 else
218 MD <= "--------";
219 end if;
220 else
221 MD <= "ZZZZZZZZ";
222 end if;
223 end process;
224
225 end Behavioral;
226
227

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