/[projet1]/users/chema/skooldaze/keyboard.s
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Contents of /users/chema/skooldaze/keyboard.s

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Revision 610 - (show annotations)
Sat Sep 10 23:40:26 2011 UTC (8 years, 6 months ago) by Chema
File size: 5194 byte(s)
More bug hunting (Symoon's) and some of the ideas from Dbug included.
1
2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3 ; Twilighte's IRQ routine!
4 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5 ; key read and timer irq
6 #define via_portb $0300
7 #define via_ddrb $0302
8 #define via_ddra $0303
9 #define via_t1cl $0304
10 #define via_t1ch $0305
11 #define via_t1ll $0306
12 #define via_t1lh $0307
13 #define via_t2ll $0308
14 #define via_t2ch $0309
15 #define via_sr $030A
16 #define via_acr $030b
17 #define via_pcr $030c
18 #define via_ifr $030D
19 #define via_ier $030E
20 #define via_porta $030f
21
22 #define ayc_Register $FF
23 #define ayc_Write $FD
24 #define ayc_Read $FE
25 #define ayc_Inactive $DD
26
27
28 .zero
29 ;irq_A .byt 0
30 ;irq_X .byt 0
31 ;irq_Y .byt 0
32
33 TimerCounter .byt 40 ;Used in music
34 zpTemp01 .byt 0
35 zpTemp02 .byt 0
36 tmprow .byt 0
37 counter .byt 0
38
39 .text
40
41 #define ROM
42 #ifdef ROM
43 #define IRQ_ADDRLO $0245
44 #define IRQ_ADDRHI $0246
45 #else
46 #define IRQ_ADDRLO $fffe
47 #define IRQ_ADDRHI $ffff
48 #endif
49
50 #define KB_SENSE_ALL_FIRST
51
52 _init_irq_routine
53 .(
54 ;Since we are starting from when the standard irq has already been
55 ;setup, we need not worry about ensuring one irq event and/or right
56 ;timer period, only redirecting irq vector to our own irq handler.
57 sei
58
59 /*
60 ; Setup DDRA, DDRB and ACR
61 lda #%11111111
62 sta via_ddra
63 lda #%11110111 ; PB0-2 outputs, PB3 input.
64 sta via_ddrb
65 lda #%1000000
66 sta via_acr
67 */
68
69 #ifdef ROM
70 ; To be Oric-1 compatible, get the
71 ; page 2 vector
72 lda $fffe
73 sta tmp
74 lda $ffff
75 sta tmp+1
76 ldy #1
77 lda #<irq_routine
78 sta (tmp),y
79 iny
80 lda #>irq_routine
81 sta (tmp),y
82 #else
83 lda #<irq_routine
84 sta $fffe
85 lda #>irq_routine
86 sta $ffff
87 #endif
88
89 lda #<9984*2
90 sta via_t1ll
91 lda #>9984*2
92 sta via_t1lh
93
94 cli
95 rts
96 .)
97
98
99 ;The IRQ routine will run at 25Hz
100 irq_routine
101 .(
102 ; Genaral purpose counter (counting fps)
103 inc counter
104
105 ;Preserve registers
106 sta sav_A+1
107 stx sav_X+1
108 sty sav_Y+1
109
110 ;Clear IRQ event
111 lda via_t1cl
112
113 ;Process keyboard
114 jsr ReadKeyboard
115
116 ;Restore Registers
117 sav_A lda #00
118 sav_X ldx #00
119 sav_Y ldy #00
120
121 ;End of IRQ
122 rti
123 .)
124
125
126
127
128 ReadKey
129 .(
130 ldx #7
131 loop
132 lda KeyBank,x
133 bne getbit
134 contsearch
135 dex
136 bpl loop
137
138 lda #0
139 rts
140
141 getbit
142 ldy #$ff
143 loop2
144 iny
145 lsr
146 bcc loop2
147 txa
148 asl
149 asl
150 asl
151 sty tmprow
152 ; Carry should be clear here
153 ;clc
154 adc tmprow
155 tay
156 lda tab_ascii,y
157 beq contsearch
158 rts
159 .)
160
161
162 oldKey .byt 0
163 ReadKeyNoBounce
164 .(
165 jsr ReadKey
166 cmp oldKey
167 beq retz
168 sta oldKey
169 tax ; Set Z flag correctly Z=0
170 rts
171 retz
172 lda #0
173 rts
174 .)
175
176
177 ReadKeyboard
178 .(
179 ;Write Column Register Number to PortA
180 lda #$0E
181 sta via_porta
182
183 ;Tell AY this is Register Number
184 lda #$FF
185 sta via_pcr
186
187 ; Clear CB2, as keeping it high hangs on some orics.
188 ; Pitty, as all this code could be run only once, otherwise
189 ldy #$dd
190 sty via_pcr
191
192 ldx #7
193
194 loop2 ;Clear relevant bank
195 lda #00
196 sta KeyBank,x
197
198 #ifdef KB_SENSE_ALL_FIRST
199 ;Write 0 to Column Register
200
201 sta via_porta
202 lda #$fd
203 sta via_pcr
204 lda #$dd
205 sta via_pcr
206
207 lda via_portb
208 and #%11111000
209 stx zpTemp02
210 ora zpTemp02
211 sta via_portb
212
213
214 ;Wait 10 cycles for circuit to settle on new row
215 ;Use time to load inner loop counter and load Bit
216
217 ; CHEMA: Fabrice Broche uses 4 cycles (lda #8:inx) plus
218 ; the four cycles of the and absolute. That is 8 cycles.
219 ; So I guess that I could do the same here (ldy,lda)
220
221 ldy #$80
222 #ifdef KB_EXTRA_NOPS
223 nop
224 nop
225 #endif
226 lda #8
227
228 ;Sense Row activity
229 and via_portb
230 beq skip2
231 #else
232 ldy #$80
233 #endif
234 ;Store Column
235 tya
236 loop1
237 eor #$FF
238
239 sta via_porta
240 lda #$fd
241 sta via_pcr
242 lda #$dd
243 sta via_pcr
244
245 lda via_portb
246 and #%11111000
247 stx zpTemp02
248 ora zpTemp02
249 sta via_portb
250
251
252 ;Use delay(10 cycles) for setting up bit in Keybank and loading Bit
253 tya
254 ora KeyBank,x
255 sta zpTemp01
256 lda #8
257
258 ;Sense key activity
259 and via_portb
260 beq skip1
261
262 ;Store key
263 lda zpTemp01
264 sta KeyBank,x
265
266 skip1 ;Proceed to next column
267 tya
268 lsr
269 tay
270 bcc loop1
271
272 skip2 ;Proceed to next row
273 dex
274 bpl loop2
275
276 rts
277 .)
278
279
280
281
282
283

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