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Contents of /users/jede/electronique/vhdl/T6502_65816/T65_Pack.vhd

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Revision 710 - (show annotations)
Tue Nov 1 12:36:41 2011 UTC (8 years, 7 months ago) by Jede
File size: 4716 byte(s)


1 -- ****
2 -- T65(b) core. In an effort to merge and maintain bug fixes ....
3 --
4 --
5 -- Ver 300 Bugfixes by ehenciak added
6 -- MikeJ March 2005
7 -- Latest version from www.fpgaarcade.com (original www.opencores.org)
8 --
9 -- ****
10 --
11 -- 65xx compatible microprocessor core
12 --
13 -- Version : 0246
14 --
15 -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
16 --
17 -- All rights reserved
18 --
19 -- Redistribution and use in source and synthezised forms, with or without
20 -- modification, are permitted provided that the following conditions are met:
21 --
22 -- Redistributions of source code must retain the above copyright notice,
23 -- this list of conditions and the following disclaimer.
24 --
25 -- Redistributions in synthesized form must reproduce the above copyright
26 -- notice, this list of conditions and the following disclaimer in the
27 -- documentation and/or other materials provided with the distribution.
28 --
29 -- Neither the name of the author nor the names of other contributors may
30 -- be used to endorse or promote products derived from this software without
31 -- specific prior written permission.
32 --
33 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
35 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
36 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
37 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 -- POSSIBILITY OF SUCH DAMAGE.
44 --
45 -- Please report bugs to the author, but before you do so, please
46 -- make sure that this is not a derivative work and that
47 -- you have the latest version of this file.
48 --
49 -- The latest version of this file can be found at:
50 -- http://www.opencores.org/cvsweb.shtml/t65/
51 --
52 -- Limitations :
53 --
54 -- File history :
55 --
56
57 library IEEE;
58 use IEEE.std_logic_1164.all;
59
60 package T65_Pack is
61
62 constant Flag_C : integer := 0;
63 constant Flag_Z : integer := 1;
64 constant Flag_I : integer := 2;
65 constant Flag_D : integer := 3;
66 constant Flag_B : integer := 4;
67 constant Flag_1 : integer := 5;
68 constant Flag_V : integer := 6;
69 constant Flag_N : integer := 7;
70
71 component T65_MCode
72 port(
73 Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
74 IR : in std_logic_vector(7 downto 0);
75 MCycle : in std_logic_vector(2 downto 0);
76 P : in std_logic_vector(7 downto 0);
77 LCycle : out std_logic_vector(2 downto 0);
78 ALU_Op : out std_logic_vector(3 downto 0);
79 Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
80 Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
81 Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
82 Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
83 BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
84 BreakAtNA : out std_logic;
85 ADAdd : out std_logic;
86 AddY : out std_logic;
87 PCAdd : out std_logic;
88 Inc_S : out std_logic;
89 Dec_S : out std_logic;
90 LDA : out std_logic;
91 LDP : out std_logic;
92 LDX : out std_logic;
93 LDY : out std_logic;
94 LDS : out std_logic;
95 LDDI : out std_logic;
96 LDALU : out std_logic;
97 LDAD : out std_logic;
98 LDBAL : out std_logic;
99 LDBAH : out std_logic;
100 SaveP : out std_logic;
101 Write : out std_logic
102 );
103 end component;
104
105 component T65_ALU
106 port(
107 Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
108 Op : in std_logic_vector(3 downto 0);
109 BusA : in std_logic_vector(7 downto 0);
110 BusB : in std_logic_vector(7 downto 0);
111 P_In : in std_logic_vector(7 downto 0);
112 P_Out : out std_logic_vector(7 downto 0);
113 Q : out std_logic_vector(7 downto 0)
114 );
115 end component;
116
117 end;

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